CY7C187
64K x 1 Static RAM
Features
Functional Description
• High speed
The CY7C187 is a high-performance CMOS static RAM
organized as 65,536 words x 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and tri-state
drivers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
— 15 ns
• CMOS for optimum speed/power
• Low active power
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A15).
— 495 mW
• Low standby power
— 110 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 22-pin (300-Mil)
Molded DIP and 24-pin (300-Mil) Molded SOJ
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pin will appear on the data output
(DOUT) pin.
The output pin stays in high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C187 utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
SOJ
Top View
DI
A0
A1
A2
A3
A4
A5
NC
A6
A7
SENSE AMPS
A12
A13
A14
A15
A0
A1
A2
A3
ROW DECODER
INPUT BUFFER
16K x 1
ARRAY
DO
CE
COLUMN DECODER
POWER
DOWN
DOUT
WE
GND
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A15
A14
A13
A12
NC
A11
A10
A9
A8
DIN
CE
C187–3
WE
A4
A5
A6
A7
A8
A9
A10
A11
1
2
3
4
5
6
7
8
9
10
11
12
DIP
Top View
A0
A1
A2
A3
A4
A5
A6
A7
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
VCC
A15
A14
A13
A12
A11
A10
A9
A8
DIN
CE
C187–2
C187–1
Selection Guide
-15
15
90
20
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05044 Rev. *A
•
198 Champion Court
•
-25
25
70
20
-35
35
70
20
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2006
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