CY7C199
32K x 8 Static RAM
Features
• High speed
— 10 ns
• Fast tDOE
• CMOS for optimum speed/power
• Low active power
— 467 mW (max, 12 ns “L” version)
• Low standby power
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
Pin Configurations
DIP / SOJ / SOIC
Top View
INPUT BUFFER
I/O1
ROW DECODER
I/O2
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
1024 x 32 x 8
ARRAY
I/O3
I/O4
I/O5
CE
WE
I/O6
POWER
DOWN
COLUMN
DECODER
I/O7
A 14
A 12
A 13
A 11
A 10
OE
OE
A1
A2
A3
A4
WE
V CC
A5
A6
A7
A8
A9
A 10
A 11
A7
A6
A5
VCC
WE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
WE
A4
A3
A2
A1
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3 2 1 28 27
4
26 A4
5
25 A3
6
24 A2
7
23 A1
8
22 OE
9
21 A0
20 CE
10
11
19 I/O7
18 I/O6
12
1314151617
I/O2
GND
I/O3
I/O4
I/O5
I/O0
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
LCC
Top View
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A0
CE
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
GND
I/O 2
I/O 1
I/O 0
A 14
A 13
A 12
Selection Guide
7C199
-8
8
120
Maximum Access Time
Maximum Operating Current
L
Maximum CMOS Standby Current
0.5
L
7C199
-10
10
110
90
0.5
0.05
7C199
-12
12
160
90
10
0.05
7C199
-15
15
155
90
10
0.05
7C199
-20
20
150
90
10
0.05
7C199
-25
25
150
80
10
0.05
7C199
-35
35
140
70
10
0.05
7C199
-45
45
140
Unit
ns
mA
10
mA
Shaded area contains advance information.
Cypress Semiconductor Corporation
Document #: 38-05160 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 7, 2003
