CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
The CY7C245A replaces bipolar devices and offers the advantages of lower power, reprogrammability, superior performance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
— 330 mW (commercial) for -25 ns
— 660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram
Pin Configurations
INIT
DIP Top View
A0
7
A1
MULTIPLEXER
A4
A5
A6
ADDRESS
DECODER
A7
A8
A9
6
O
8-BIT
EDGETRIGGERED
REGISTER
5
O
4
O
3
O
COLUMN
ADDRESS
2
O
A10
1
D
CP
A4
A3
A2
A1
A0
NC
O0
0
C
Q
VCC
A8
A9
A10
INIT
E/ES
CP
O7
O6
O5
O4
O3
4 3 2 1 282726
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
121314151617
A10
INIT
E/ES
CP
NC
O7
O6
O1
O2
GND
NC
O3
O4
O5
E/E S
24
23
22
21
20
19
18
17
16
15
14
13
LCC/PLCC (Opaque only) Top View
O
CP
PROGRAMMABLE
MULTIPLEXER
1
2
3
4
5
6
7
8
9
10
11
12
A5
A6
A7
NC
V
CC
A8
A9
A3
O
PROGRAMMABLE
ARRAY
ROW
ADDRESS
PROGRAMMABLE
INITIALIZE WORD
A2
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
O
Selection Guide
7C245A-15
7C245A-18
Minimum Address Set-up Time
15
18
25
35
ns
Maximum Clock to Output
10
12
12
15
ns
120
120
90
90
mA
120
120
120
mA
Maximum Operating Current Standard
Commercial
Military
Cypress Semiconductor Corporation
Document #: 38-04007 Rev. *E
•
198 Champion Court
•
7C245A-25
7C245A-35
Unit
San Jose, CA 95134-1709
•
408-943-2600
Revised August 17, 2006
