CY7C261
CY7C263/CY7C264
8K x 8 Power-Switched and Reprogrammable PROM
Features
Functional Description
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
The CY7C261, CY7C263, and CY7C264 are high-performance 8192-word by 8-bit CMOS PROMs. When deselected,
the CY7C261 automatically powers down into a low-power
standby mode. It is packaged in a 300-mil-wide package. The
CY7C263 and CY7C264 are packaged in 300-mil-wide and
600-mil-wide packages respectively, and do not power down
when deselected. The reprogrammable packages are
equipped with an erasure window; when exposed to UV light,
these PROMs are erased and can then be reprogrammed.
The memory cells utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
— 20 ns (Commercial)
— 25 ns (Military)
• Low power
— 660 mW (Commercial)
— 770 mW (Military)
• Super low standby power (7C261)
— Less than 220 mW when deselected
Read is accomplished by placing an active LOW signal on CS.
The contents of the memory location addressed by the
address line (A0−A12) will become available on the output lines
(O0−O7).
Logic Block Diagram
Pin Configurations
A0
O7
A1
A2
A3
ROW
ADDRESS
PROGRAMMABLE
ARRAY
COLUMN
MULTIPLEXER
DIP/Flatpack
Top View
O6
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
A4
A5
O5
A6
A7
ADDRESS
DECODER
O4
A8
O3
A9
A10
A11
COLUMN
ADDRESS
O2
O2
GND
A12
1
24
23
2
3
22
4
21
5
20
6
19
7
18
8 7C261 17
7C263
9 7C264 16
10
15
11
14
12
13
VCC
A8
A9
A10
CS
A11
A12
O7
O6
O5
O4
O3
LCC/PLCC (OpaqueOnly)
Top View
A5
A6
A7
NC
VCC
A8
A9
•
•
A4
A3
A2
A1
A0
NC
O0
4 3 2 1 28 27 26
25
5
24
6
23
7C261
7
22
8
7C263
21
9
20
10
19
11
12 1314151617 18
A10
CS
A11
A12
NC
O7
O6
O1
O2
GND
NC
O3
O4
O5
•
•
•
•
— Fast access: 20 ns
EPROM technology 100% programmable
Slim 300-mil or standard 600-mil packaging available
5V ± 10% VCC, commercial and military
Capable of withstanding greater than 2001V static
discharge
TTL-compatible I/O
Direct replacement for bipolar PROMs
The CY7C261, CY7C263, and CY7C264 are plug-in replacements for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requires only 12.5V for the supervoltage and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming the product will meet DC and AC specification
limits.
O1
POWER DOWN
(7C261)
O0
CS
For an 8K x 8 Registered PROM, see theCY7C265.
Cypress Semiconductor Corporation
Document #: 38-04010 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 17, 2006
