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DM54L73W
DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops after a complete clock pulse While the clock is low the slave is isolated from the master On the positive transition of the clock the data from the J and K inputs is transferred to the master While the clock is high the data from the J and K inputs are disabled On the negative transition of the clock the data from the master is transferred to the slave The logic states of the J and K inputs must not be allowed to change while the clock is high Data is transferred to the outputs on the falling edge of the clock pulse A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs Connection Diagram Dual-In-Line Package TL F 6630 – 1 Order Number DM54L73J or DM54L73W See NS Package Number J14A or W14B Function Table Inputs Outputs CLR CLK J K L H H H H X X L H L H X L L H H Q Q L H QO QO H L L H Toggle H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level e Positive pulse data The J and K inputs must be held constant while the clock is high Data is transferred to the outputs on the falling edge of the clock pulse QO e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each complete high level clock pulse C1995 National Semiconductor Corporation TL F 6630 RRD-B30M105 Printed in U S A DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1989
NS
National Semiconductor Corporation 日本ではナショセミと略称されていたが2011年9月23日、米TI社に買収され、同社のシリコンバレー部門となった。
TI
Texas Instruments Incorporated
U.S.A
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