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DP8409AN
DP8409A Multi-Mode Dynamic RAM Controller Driver General Description Operational Features Dynamic memory system designs which formerly required several support chips to drive the memory array can now be implemented with a single IC the DP8409A MultiMode Dynamic RAM Controller Driver The DP8409A is capable of driving all 16k and 64k Dynamic RAMs (DRAMs) as well as 256k DRAMs Since the DP8409A is a one-chip solution (including capacitive-load drivers) it minimizes propagation delay skews the major performance disadvantage of multiple-chip memory drive and control The DP8409A’s 8 modes of operation offer a wide selection of DRAM control capabilities Memory access may be controlled externally or on-chip automatically an on-chip refresh counter makes refreshing (either externally or automatically controlled) less complicated and automatic memory initialization is both simple and fast The DP8409A is a 48-pin DRAM Controller Driver with 9 multiplexed address outputs and 6 control signals It consists of two 9-bit address latches a 9-bit refresh counter and control logic All output drivers are capable of driving 500 pF loads with propagation delays of 25 ns The DP8409A timing parameters are specified driving the typical load capacitance of 88 DRAMs including trace capacitance The DP8409A has 3 mode-control pins M2 M1 and M0 where M2 is in general REFRESH These 3 pins select 8 modes of operation Inputs B1 and B0 in the memory access modes (M2 e 1) are select inputs which select one of four RAS outputs During normal access the 9 address outputs can be selected from the Row Address Latch or the Column Address Latch During refresh the 9-bit on-chip refresh counter is enabled onto the address bus and in this mode all RAS outputs are selected while CAS is inhibited The DP8409A can drive up to 4 banks of DRAMs with each bank comprised of 16k’s 64k’s or 256k’s Control signal outputs RAS CAS and WE are provided with the same drive capability Each RAS output drives one bank of DRAMs so that the four RAS outputs are used to select the banks while CAS WE and the multiplexed addresses can be connected to all of the banks of DRAMs This leaves the non-selected banks in the standby mode (less than one tenth of the operating power) with the data outputs in TRISTATE Only the bank with its associated RAS low will be written to or read from Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y All DRAM drive functions on one chip minimizes skew on outputs maximizes AC peformance On-chip capacitive-load drives (specified to drive up to 88 DRAMs) Drives directly all 16k 64k and 256k DRAMs Capable of addressing 64k 256k or 1M words Propagation delays of 25 ns typical at 500 pF load CAS goes low automatically after column addresses are valid if desired Auto Access mode provides RAS row to column select then CAS automatically and fast WE follows WIN unconditionally offering READ WRITE or READ-MODIFY-WRITE cycles On-chip 9-bit refresh counter with selectable End-ofCount (127 255 or 511) End-of-Count indicated by RF I O pin going low at 127 255 or 511 Low input on RF I O resets 9-bit refresh counter CAS inhibited during refresh cycle Fall-through latches on address inputs controlled by ADS TRI-STATE outputs allow multi-controller addressing of memory Control output signals go high-impedance logic ‘‘1’’ when disabled for memory sharing Power-up counter reset control signals high address outputs TRI-STATE and End-of-Count set to 127 Mode Features Y Y Y Y Y Y Y Y Y Y 8 modes of operation 3 access 3 refresh and 2 set-up 2 externally controlled modes 1 access and 1 refresh (Modes 0 4) 2 auto-access modes RAS x R C x CAS automatic with tRAH e 20 or 30 ns minimum (Modes 5 6) Auto-access mode allows Hidden Refreshing (Mode 5) Forced Refresh requested on RF I O if no Hidden Refresh (Mode 5) Forced Refresh performed after system acknowledge of request (Mode 1) Automatic Burst Refresh mode stops at End-of-Count of 127 255 or 511 (Mode 2) 2 All-RAS Acces modes externally or automatically controlled for memory initialization (Modes 3a 3b) Automatic All-RAS mode with external 8-bit counter frees system for other set-up routines (Mode 3a) End-of-Count value of Refresh Counter set by B1 and B0 (Mode 7) TL F 8409 – 1 TRI-STATE is a registered trademark of National Semiconductor Corp PAL is a registered trademark of and used under license with Monolithic Memories Inc C1995 National Semiconductor Corporation TL F 8409 RRD-B30M105 Printed in U S A DP8409A Multi-Mode Dynamic RAM Controller Driver May 1989
NS
National Semiconductor Corporation 日本ではナショセミと略称されていたが2011年9月23日、米TI社に買収され、同社のシリコンバレー部門となった。
TI
Texas Instruments Incorporated
U.S.A
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