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DSP56001A/D, Rev. 1
SEMICONDUCTOR TECHNICAL DATA
DSP56001A
Product Preview
24-BIT DIGITAL SIGNAL PROCESSOR
The DSP56001A is an MPU-style general purpose Digital Signal Processor (DSP) composed of an
efficient 24-bit DSP core, program and data memories, various peripherals, and support
circuitry. The DSP56000 core is fed by on-chip Program RAM, two independent data RAMs, and
two data ROMs containing sine, A-law, and µ-law tables. The DSP56001A contains a Serial
Communication Interface (SCI), a Synchronous Serial Interface (SSI), and a parallel Host Interface
(HI). This combination of features, illustrated in Figure 1, makes the DSP56001A a cost-effective,
high-performance solution for high-precision general purpose digital signal processing. The
DSP56001A is intended as a replacement for the DSP56001. The DSP56002 should be considered for
new designs.
6
3
Sync.
Serial
(SSI)
or I/O
Serial
Comm.
(SCI)
or I/O
Host
Interface
(HI)
or I/O
16-bit Bus
24-bit Bus
15
X Data
Memory
256 × 24 RAM
256 × 24 ROM
Y Data
Memory
256 × 24 RAM
256 × 24 ROM
(boot)
24-bit
56000 DSP
Core
Program
Memory
512 × 24 RAM
64 × 24 ROM
(A-law/µ-law)
(sine)
PAB
Address
Generation
Unit
XAB
YAB
External
Address
Bus
Switch
Address
16
GDB
Internal
Data
Bus
Switch
Clock
Generator
PDB
XDB
YDB
Interrupt
Control
2
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
Bus
Control
Data
24
Control
7
Program Control Unit
2
AA0884
IRQ
Figure 1 DSP56001A Block Diagram
©1997 MOTOROLA, INC.
External
Data
Bus
Switch
