MOTOROLA Freescale Semiconductor, Inc.
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DSP56002/D, Rev. 3
SEMICONDUCTOR TECHNICAL DATA
DSP56002
24-BIT DIGITAL SIGNAL PROCESSOR
Freescale Semiconductor, Inc...
The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an
efficient 24-bit DSP core, program and data memories, various peripherals, and support
circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs.
The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI),
parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip
Emulation (OnCE™) port. This combination of features, illustrated in Figure 1, makes the
DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital
signal processing.
1
6
24-bit
Timer/
Event
Counter
Sync.
Serial
(SSI)
or I/O
3
Serial
Comm.
(SCI)
or I/O
XAB
YAB
External
Data
Bus
Switch
PDB
XDB
YDB
Interrupt
Control
Clock
Gen.
Program
Decode
Controller
Program
Address
Generator
Y Data
Memory
256 × 24 RAM
256 × 24 ROM
(sine)
External
Address
Bus
Switch
GDB
OnCE™
Port
7
X Data
Memory
256 × 24 RAM
256 × 24 ROM
(A-law/ µ-law)
PAB
Internal
Data
Bus
Switch
PLL
Program
Memory
512 × 24 RAM
64 × 24 ROM
(boot)
Host
Interface
(HI)
or I/O
Address
Generation
Unit
24-bit
56000 DSP
Core
16-bit Bus
24-bit Bus
15
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
Bus
Control
Address
16
Data
24
Control
10
Program Control Unit
4
3
IRQ
AA0604
Figure 1 DSP56002 Block Diagram
©1996 MOTOROLA, INC.
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