APEX 20KC
Programmable Logic
Device
®
February 2004 ver. 2.2
Features...
Data Sheet
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Programmable logic device (PLD) manufactured using a 0.15-µm alllayer copper-metal fabrication process
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25 to 35% faster design performance than APEXTM 20KE devices
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Pin-compatible with APEX 20KE devices
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High-performance, low-power copper interconnect
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MultiCoreTM architecture integrating look-up table (LUT) logic
and embedded memory
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LUT logic used for register-intensive functions
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Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
High-density architecture
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200,000 to 1 million typical gates (see Table 1)
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Up to 38,400 logic elements (LEs)
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Up to 327,680 RAM bits that can be used without reducing
available logic
Table 1. APEX 20KC Device Features
Feature
Note (1)
EP20K200C
EP20K400C
EP20K600C
EP20K1000C
Maximum system gates
526,000
1,052,000
1,537,000
1,772,000
Typical gates
200,000
400,000
600,000
1,000,000
8,320
16,640
24,320
38,400
LEs
ESBs
Maximum RAM bits
PLLs (2)
52
104
152
160
106,496
212,992
311,296
327,680
2
4
4
4
-7, -8, -9
-7, -8, -9
-7, -8, -9
-7, -8, -9
Maximum macrocells
832
1,664
2,432
2,560
Maximum user I/O pins
376
488
588
708
Speed grades (3)
Notes to Table 1:
(1)
(2)
(3)
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
PLL: phase-locked loop.
The -7 speed grade provides the fastest performance.
Altera Corporation
DS-APEX20KC-2.2
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