MAX 5000
Programmable Logic
Device Family
®
May 1999, ver. 5
Features...
Data Sheet
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Advanced Multiple Array MatriX (MAX®) 5000 architecture
combining speed and ease-of-use of PAL devices with the density of
programmable gate arrays
Complete family of high-performance, erasable CMOS EPROM
erasable programmable logic devices (EPLDs) for designs ranging
from fast 28-pin address decoders to 100-pin LSI custom peripherals
600 to 3,750 usable gates (see Table 1)
Fast, 15-ns combinatorial delays and 76.9-MHz counter frequencies
Configurable expander product-term distribution allowing more
than 32 product terms in a single macrocell
28 to 100 pins available in dual in-line package (DIP), J-lead chip
carrier, pin-grid array (PGA), and quad flat pack (QFP) packages
Programmable registers providing D, T, JK, and SR flipflop
functionality with individual clear, preset, and clock controls
Programmable security bit for protection of proprietary designs
Software design support featuring the Altera® MAX+PLUS® II
development system on Windows-based PCs, as well as
Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations
Table 1. MAX 5000 Device Features
Feature
EPM5064
EPM5128
EPM5130
EPM5192
Usable gates
600
1,250
2,500
2,500
3,750
Macrocells
32
64
128
128
192
Logic array blocks (LABs)
1
4
8
8
12
Expanders
64
128
256
256
384
Routing
Global
PIA
PIA
PIA
PIA
Maximum user I/O pins
24
36
60
84
72
t PD (ns)
15
25
25
25
25
t ASU (ns)
4
4
4
4
4
t CO (ns)
10
14
14
14
14
76.9
50
50
50
50
f CNT (MHz)
Altera Corporation
A-DS-M5000-05
9
MAX 5000
EPM5032
709
