FLASHlogic
Programmable Logic
Device Family
®
June 1996, ver. 2
Features...
Data Sheet
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High-performance programmable logic device (PLD) family
– SRAM-based logic with shadow FLASH memory elements
fabricated on advanced CMOS technology
– Logic densities from 1,600 to 3,200 usable gates (see Table 1)
– Combinatorial speeds with tPD as low as 10 ns
– Counter frequencies of up to 80 MHz
8 to 16 logic array blocks (LABs) linked by a 100%-connectable
programmable interconnect array (PIA) for improved fitting of
complex designs
24V10 macrocell features available
– Dual feedback on all I/O pins
– Product-term allocation matrix supporting up to 16 product
terms per macrocell
– Programmable registers providing D, T, SR, and JK flipflop
functionality with clear, preset, and clock controls
– Fast 12-bit identity compare option
Fully compliant with PCI Local Bus Specification, version 2.1
Table 1. FLASHlogic Device Features
Feature
EPX880
EPX8160
Usable gates
1,600
3,200
Maximum SRAM bits
10,240
20,480
Macrocells
80
160
Logic array blocks (LABs)
8
16
Package options
(maximum user I/O pins)
84-pin PLCC (62)
132-pin PQFP (104)
208-pin PQFP (172)
tPD (ns)
A-DS-FLSH-02
10
6
6
fCNT (MHz)
Altera Corporation
10
tCO (ns)
80
80
265
