Intel® i960® RX I/O Processor at 3.3 Volts
Datasheet
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33 MHz, 3.3 Volt Version (80960RP 33/3.3)
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66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core
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Complies with PCI Local Bus Specification, Revision 2.1
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5 Volt PCI Signalling Environment
Product Features
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High Performance 80960JF Core
—Sustained One Instruction/Clock Execution
— 4 Kbyte, 2-Way Set-Associative
Instruction Cache
— 2 Kbyte Direct-Mapped Data Cache
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
—Programmable Bus Widths: 8-, 16-, 32-Bit
— 1 Kbyte Internal Data RAM
— Local Register Cache
(Eight Available Stack Frames)
— Two 32-Bit On-Chip Timer Units
PCI-to-PCI Bridge Unit
— Primary and Secondary PCI Interfaces
— Two 64-Byte Posting Buffers
— Delayed and Posted Transaction Support
— Forwards Memory, I/O, Configuration
Commands from PCI Bus to PCI Bus
Two Address Translation Units
— Connects Local Bus to PCI Buses
— I/O Address Translation Support
— Direct Outbound Addressing Support
Messaging Unit
— Four Message Registers
— Two Doorbell Registers
— Four Circular Queues
— 1004 Index Registers
Memory Controller
— 256 Mbytes of 32- or 36-Bit DRAM
— Interleaved or Non-Interleaved DRAM
— Fast Page-Mode DRAM Support
— Extended Data Out and Burst
— Extended Data Out DRAM Support
—Two Independent Banks for SRAM /
ROM / Flash (16 Mb/Bank; 8- or 32-Bit)
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DMA Controller
— Three Independent Channels
— PCI Memory Controller Interface
— 32-Bit Local Bus Addressing
— 64-Bit PCI Bus Addressing
— Independent Interface to Primary and
Secondary PCI Buses
— 132 Mbyte/sec Burst Transfers to PCI
and Local Buses
— Direct Addressing to and from PCI
Buses
— Unaligned Transfers Supported in
Hardware
— Two Channels Dedicated to Primary
PCI Bus
— One Channel Dedicated to Secondary
PCI Bus
I/O APIC Bus Interface Unit
— Multiprocessor Interrupt Management
for Intel Architecture CPUs (Pentium®
and Pentium® Pro Processors)
— Dynamic Interrupt Distribution
— Multiple I/O Subsystem Support
I2C Bus Interface Unit
— Serial Bus
— Master/Slave Capabilities
— System Management Functions
Secondary PCI Arbitration Unit
— Supports Six Secondary PCI Devices
— Multi-priority Arbitration Algorithm
— External Arbitration Support Mode
Private PCI Device Support
SuperBGA* Package
— 352 Ball-Grid Array (HL-PBGA)
Document Number: 273001-003
August, 2001
