Preliminary
GS88218/36B-11/11.5/100/80/66
119-Bump BGA
Commercial Temp
Industrial Temp
512K x 18, 256K x 36 ByteSafe™ 100 MHz–66 MHz
3.3 V VDD
8Mb S/DCD Sync Burst SRAMs 3.3 V and 2.5 V I/O
Features
on every cycle with no degradation of chip performance.
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect Selectable
• IEEE 1149.1 JTAG Compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• ZQ mode pin for user-selectable high/low output drive strength
• x16/x32 mode with on-chip parity encoding and error detection
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipelined mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 119-bump BGA package
-11
-11.5
-100
-80
-66
10 ns
10 ns 12.5 ns 15 ns
Pipeline tCycle 10 ns
4.0 ns 4.0 ns 4.0 ns 4.5 ns
5 ns
3-1-1-1
tKQ
IDD 225 mA 225 mA 225 mA 200 mA 185 mA
Flow Through/Pipeline Reads
Flow
Through
2-1-1-1
The function of the Data Output Register can be controlled by
the user via the FT mode bump (Bump 5R). Holding the FT
mode pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS88218/36B is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input on Bump 4L.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
11 ns 11.5 ns 12 ns
14 ns
18 ns
tKQ
15 ns
15 ns
15 ns
15 ns
20 ns
tCycle
180 mA 180 mA 180 mA 175 mA 165 mA
IDD
Functional Description
ByteSafe™ Parity Functions
Applications
The GS88218/36B features ByteSafe data security functions.
See “ByteSafe™ Parity Functions” on page 8 for further
information.
The GS88218/36B is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart on page 38 for details.
Controls
Addresses, data I/Os, chip enables (E1 and E2), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
Rev: 1.15 5/2001
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS88218/36B operates on a 3.3 V power supply and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (VDDQ) pins are used to decouple output noise
from the internal circuit.
1/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2000, Giga Semiconductor, Inc.
