HY29LV160
16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory
KEY FEATURES
n Single Power Supply Operation
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– Read, program and erase operations from
2.7 to 3.6 volts
– Ideal for battery-powered applications
High Performance
– 70, 80, 90 and 120 ns access time
versions
Ultra-low Power Consumption (Typical
Values At 5 Mhz)
– Automatic sleep mode current: 1 µA
– Standby mode current: 1 µA
– Read current: 9 mA
– Program/erase current: 20 mA
Flexible Sector Architecture:
– One 16 KB, two 8 KB, one 32 KB and
thirty-one 64 KB sectors in byte mode
– One 8 KW, two 4 KW, one 16 KW and
thirty-one 32 KW sectors in word mode
– Top or bottom boot block configurations
available
Sector Protection
– Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
– Sectors lockable in-system or via
programming equipment
– Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
Fast Program and Erase Times
– Sector erase time: 0.25 sec typical for
each sector
– Chip erase time: 8 sec typical
– Byte program time: 9 µs typical
Unlock Bypass Program Command
– Reduces programming time when issuing
multiple program command sequences
Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
Erase Suspend/Erase Resume
– Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
– Erase Resume can then be invoked to
complete suspended erasure
Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
Preliminary
Revision 1.1, July 2000
n 100,000 Write Cycles per Sector Minimum
n Data# Polling and Toggle Bits
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– Provide software confirmation of
completion of program and erase
operations
Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
Compliant With Common Flash Memory
Interface (CFI) Specification
– Flash device parameters stored directly
on the device
– Allows software driver to identify and use
a variety of different current and future
Flash products
Compatible With JEDEC standards
– Pinout and software compatible with
single-power supply Flash devices
– Superior inadvertent write protection
Space Efficient Packaging
– 48-pin TSOP and 48-ball FBGA packages
LOGIC DIAGRAM
20
8
A[19:0]
DQ[7:0]
7
CE#
DQ[14:8]
OE#
DQ15/A-1
WE#
RY/BY#
RESET#
BYTE#
