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Preliminary
IBM043610QLAB
IBM041810QLAB
32K X 36 & 64K X 18 SRAM
Features
• 32K x 36 or 64K x 18 Organizations
• Common I/O
• 0.5 Micron CMOS Technology
• Asynchronous Output Enable and Power Down
Inputs
• Synchronous Flow-Thru Mode Of Operation
with Self-Timed Late Write
• Dual Differential Input and Output Clocks
• Single +3.3V Power Supply and Ground
• Boundary Scan using limited set of JTAG 1149.1
functions
• Byte Write Capability & Global Write Enable
• GTL/HSTL Input and Output levels
• 7 X 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• Registered Addresses, Write Enables, Sync
Select and Data Ins.
• Programmable Impedance Output Drivers
Description
The IBM043610QLA and IBM04180QLA 1Mb
SRAMS are Synchronous Flow-Thru Mode, high
performance CMOS Static Random Access Memories that are versatile, wide I/O, and achieve 5 nanosecond cycle times. Dual differential K clocks are
used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of
the K Clock, all Addresses, Write-Enables, Sync
Select and Data Ins are registered internally. Differential clocks C and C are used to control the Output
Data Hold Time by allowing output data to change
after the rising edge of the C clock. An internal Write
buffer allows write data to follow one cycle after
addresses and controls. The chip is operated with a
single +3.3V power supply and is compatible with
GTL/HSTL I/O interfaces.
03H9038
SA14-4657-05
Revised 5/97
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
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