IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
64-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT
DESCRIPTION:
FEATURES:
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IDT49C465
IDT49C465A
32-bit wide Flow-thruEDC™ unit, cascadable to 64 bits
Single-chip 64-bit Generate Mode
Separate system and memory buses
On-chip pipeline latch with external control
Supports bidirectional and common I/O memories
Corrects all single-bit errors
Detects all double-bit errors and some multiple bit errors
Error Detection Time — 12ns
Error Correction Time — 14ns
On chip diagnostic registers
Parity generation and checking on system data bus
Low power CMOS — 100mA typical at 20MHz
144-pin PGA and PQFP packages
The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC unit. The
chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. It can be expanded to 64-bit
widths by cascading two units, without the need for additional external
logic. The Flow-thruEDC has been optimized for speed and simplicity
of control.
The EDC unit has been designed for use in either of two configurations in an error correcting memory system. The bidirectional configuration is most appropriate for systems using bidirectional memory
buses. A second system configuration utilizes external octal buffers,
and is well-suited for systems using memory with separate I/O buses.
The IDT49C465/A supports partial word writes, pipelining, and error
diagnostics. It also provides parity protection for data on the system
side.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
M D 0-31
Correct
Logic
M em ory
Checkbit
Generator
Syndrom e
G enerator
MD
Latch
Checkbit
Latch
CBI 0-7
ERR
Expansion
Logic
MLE
Mux
Detect
Logic
MERR
Pipeline
Latch
PCBI 0-7
SD 0-31
CONTROL
CONTROL
SD
Latch
Byte
M ux
System
Checkbit
Generator
SLE
PLE
M ux
CBO 0-7
CONTROL
CONTROL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
NOVEMBER 2000
1
c
1999 Integrated Device Technology, Inc.
DSC-2552/9