CY62148B MoBL™
4-Mbit (512K x 8) Static RAM
Features
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE), and three-state drivers. This device
has an automatic power-down feature that reduces power
consumption by more than 99% when deselected.
• High Speed: 70 ns
• 4.5V–5.5V operation
• Low active power
— Typical active current: 2.5 mA @ f = 1 MHz
— Typical active current: 12.5 mA @ f = fmax(70 ns)
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• CMOS for optimum speed/power
• Available in standard 32-lead (450-mil) SOIC, 32-lead
TSOP II and 32-lead Reverse TSOP II packages
Functional Description
The CY62148B is a high-performance CMOS static RAM
organized as 512K words by 8 bits. Easy memory expansion
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148B is available in a standard 32-pin 450-mil-wide
body width SOIC, 32-pin TSOP II, and 32-pin Reverse TSOP
II packages.
Logic Block Diagram
Pin Configuration
Top View
SOIC
TSOP II
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
I/O0
INPUT BUFFER
CE
I/O1
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A4
A5
A6
A7
A12
A14
A16
A17
512 K x 8
ARRAY
I/O3
I/O4
POWER
DOWN
A2
A3
A15
A18
A13
A8
A9
A11
A10
OE
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
A16
A17
I/O6
I/O7
WE
Cypress Semiconductor Corporation
Document #: 38-05039 Rev. *C
•
198 Champion Court
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
Top View
Reverse
TSOP II
I/O5
COLUMN
DECODER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
•
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
OE
A11
A9
A8
A13
WE
A18
A15
Vcc
San Jose, CA 95134-1709
•
408-943-2600
Revised August 2, 2006
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