HIGH SPEED 64K (4K X 16 BIT)
IDT70824S/L
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
Features
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High-speed access
– Military: 35/45ns (max.)
– Commercial: 20/25/35/45ns (max.)
Low-power operation
– IDT70824S
Active: 775mW (typ.)
Standby: 5mW (typ.)
– IDT70824L
Active: 775mW (typ.)
Standby: 1mW (typ.)
4K x 16 Sequential Access Random Access Memory (SARAM™)
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
Random Access Port
High speed operation
– 20ns tAA for random access port
– 20ns tCD for sequential port
– 25ns clock cycle time
Architecture based on Dual-Port RAM cells
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Compatible with Intel BMIC and 82430 PCI Set
Width and Depth Expandable
Sequential side
– Address based flags for buffer control
– Pointer logic supports up to two internal buffers
Battery backup operation - 2V data retention
TTL-compatible, single 5V (+10%) power supply
Available in 80-pin TQFP and 84-pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Description
The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random
Access Memory (SARAM). The SARAM offers a single-chip solution to
buffer data sequentially on one port, and be accessed randomly (asynchronously) through the other port. The device has a Dual-Port RAM
based architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with counter se-
Functional Block Diagram
12
A0-11
CE
OE
R/W
LB LSB
MSB
UB
CMD
Random
Access
Port
Controls
Sequential
Access
Port
Controls
4K X 16
Memory
Array
16
I/O0-15
DataL
12
AddrL
16
DataR
16
RST
SCLK
CNTEN
SOE
SSTRT1
SSTRT2
SCE
SR/W
SLD
AddrR
12
Reg.
12
SI/O0-15
,
RST
12
12
Pointer/
Counter
12
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
Flag Status
EOB1
12
COMPARATOR
EOB2
3099 drw 01
MAY 2000
1
©2000 Integrated Device Technology, Inc.
DSC-3099/5
6.07
