IDT71321SA/LA
HIGH SPEED
IDT71421SA/LA
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
Features
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High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71321/421LA
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
Two INT flags for port-to-port communications
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MASTER IDT71321 easily expands data bus width to 16-ormore-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
(1,2)
BUSYL
A10L
A0L
BUSYR
Address
Decoder
MEMORY
ARRAY
11
CEL
OEL
R/WL
Address
Decoder
A10R
A0R
11
ARBITRATION
and
INTERRUPT
LOGIC
CER
OER
R/WR
(2)
(2)
INTR
INTL
2691 drw 01
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
AUGUST 2006
1
©2006 Integrated Device Technology, Inc.
DSC-2691/12
