®
ispLSI 2128VL
Functional Block Diagram*
Output Routing Pool (ORP)
Output Routing Pool (ORP)
• 2.5V LOW VOLTAGE 2128 ARCHITECTURE
— Interfaces with Standard 3.3V Devices (Inputs and
I/Os are 3.3V Tolerant)
— 125 mA Typical Active Current
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
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fmax = 150 MHz Maximum Operating Frequency
tpd = 6.0 ns Propagation Delay
D5
D4
D1
D0
C7
A1
C6
D
Logic
Array
A4
Q
D
Q
D
A3
Q
D
A2
Q
C5
C4
GLB
C3
C2
A5
C1
A6
Global Routing Pool (GRP)
A7
B1
B2
B3
Output Routing Pool (ORP)
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
D2
A0
B0
*128 I/O version shown
B4
B5
C0
B6
B7
Output Routing Pool (ORP)
0139A/2128VL
Description
• IN-SYSTEM PROGRAMMABLE
The ispLSI 2128VL is a High Density Programmable
Logic Device available in 128 and 64 I/O-pin versions.
The device contains 128 Registers, eight Dedicated
Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2128VL features in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2128VL offers nonvolatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
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D3
D6
Output Routing Pool (ORP)
Output Routing Pool (ORP)
6000 PLD Gates
128 and 64 I/O Pin Versions, Eight Dedicated Inputs
128 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2128V and 2128VE Devices
Output Routing Pool (ORP)
D7
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Output Routing Pool (ORP)
• SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
CLK 0
CLK 1
CLK 2
Features
Enhanced Pin Locking Capability
Three Dedicated Clock Input Pins
Synchronous and Asynchronous Clocks
Programmable Output Slew Rate Control
Flexible Pin Placement
Optimized Global Routing Pool Provides Global
Interconnectivity
The basic unit of logic on the ispLSI 2128VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2128vL_03
1
January 2002
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
2.5V In-System Programmable
SuperFAST™ High Density PLD