KM416C1000C, KM416C1200C
KM416V1000C, KM416V1200C
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CASbefore-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Fast Page Mode operation
• Part Identification
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
- KM416C1000C/C-L (5V, 4K Ref.)
- KM416C1200C/C-L (5V, 1K Ref.)
- KM416V1000C/C-L (3.3V, 4K Ref.)
- KM416V1200C/C-L (3.3V, 1K Ref.)
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• Active Power Dissipation
• JEDEC Standard pinout
Unit : mW
3.3V
Speed
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
5V
4K
1K
4K
1K
400mil packages
• Single +5V±10% power supply (5V product)
-5
324
504
495
770
• Single +3.3V±0.3V power supply (3.3V product)
-6
288
468
440
715
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
VCC
C1000C
5V
V1000C
5V
V1200C
Refresh period
Normal
3.3V
C1200C
Refresh
cycle
L-ver
RAS
UCAS
LCAS
W
Control
Clocks
3.3V
4K
64ms
Lower
Data in
Buffer
128ms
1K
Refresh Timer
16ms
Row Decoder
Refresh Control
Refresh Counter
• Perfomance Range
Speed
Vcc
Vss
VBB Generator
tRAC
tCAC
tRC
tPC
Remark
-5
50ns
15ns
90ns
35ns
5V/3.3V
-6
60ns
15ns
110ns
40ns
5V/3.3V
A0-A11
(A0 - A9)*1
A0 - A7
(A0 - A9)*1
Memory Array
1,048,576 x16
Cells
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 1K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
