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KM416S4030BT-F10

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KM416S4030B CMOS SDRAM Revision History Revision .1(November 1997) - tRDL has changed 10ns to 12ns. - Binning -10 does not meet PC100 characteristics . So AC parameter/Characteristics have changed to 64M 2nd values. Revision .2 (February 1998) - Input leakage Currents (Inputs / DQ) are changed. IIL(Inputs) : ± 5uA to ± 1uA, IIL(DQ) : ± 5uA to ± 1.5uA. - The measuring condition of tR/tF is clearly defined each as 0pF +50Ω to VSS/VDD, 50pF +50Ω to VSS/VDD - Cin to be measured at VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ±200 mV. - AC Operating Condition is changed as defined : VIH(max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. VIL(min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. - ICC3PS is changed 1mA to 2mA. - ICC6 for Low power is changed 400uA to 450uA. - ICC4 value is changed. Revision .3 (March 1998) - ICC2N, ICC2NS, ICC3N & ICC3NS values are changed. Revision .4 (June 1998) - tSH (-10 binning) is revised. REV. 4 June '98

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