KM44C1003D
CMOS DRAM
1M x 4bit CMOS Quad CAS DRAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 4bit Fast Page Mode Quad CAS CMOS DRAMs. Fast Page Mode offers high speed random access of
memory cells within the same row. Access time (-5, -6 or -7), power consumption(Normal), and package type (SOJ or TSOP-II) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. All
inputs and outputs are fully TTL compatible and four seperate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode. This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high
band-width, low power consumption and high reliability.
• Fast Page Mode operation
FEATURES
• Four seperate CAS pins provide for seperate I/O
• Part Identification
operation
• CAS-before-RAS refresh capability
- KM44C1003D(5V)
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL compatible inputs and outputs
• Active Power Dissipation
• Early Write or output enable controlled write
Unit : mW
Speed
Active power dissipation
-5
470
-6
415
-7
• JEDEC Standard pinout
360
• Available in 26(24)-pin SOJ 300mil and TSOP(II)
300mil packages
• Single +5V±10% power supply
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Part
NO.
Refresh
cycle
Refresh Period
KM44C1003D
1K
RAS
CAS0~3
W
Control
Clocks
16ms
Vcc
Vss
VBB Generator
Normal
Row Decoder
Refresh Control
Refresh Counter
• Performance Range
Speed
tRAC
tCAC
tRC
tPC
-5
50ns
15ns
90ns
35ns
-6
60ns
15ns
110ns
40ns
-7
70ns
20ns
130ns
Memory Array
1,048,576 x 4
Cells
45ns
Row Address Buffer
A0~A9
Col. Address Buffer
Column Decoder
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Refresh Timer
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
