SN54LVTZ240, SN74LVTZ240
3.3ĆV ABT OCTAL BUFFERS/DRIVERS
WITH 3ĆSTATE OUTPUTS
SCBS301B − SEPTEMBER 1993 − REVISED JULY 1995
D State-of-the-Art Advanced BiCMOS
D
D
D
D
D
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54LVTZ240 . . . FK PACKAGE
(TOP VIEW)
1A2
2Y3
1A3
2Y2
1A4
description
4
3 2 1 20 19
18
5
17
6
16
7
15
8
9 10 11 12 13
14
1Y1
2A4
1Y2
2A3
1Y3
2Y1
GND
2A1
1Y4
2A2
These octal buffers and line drivers are designed
specifically for low-voltage (3.3-V) VCC operation,
but with the capability to provide a TTL interface
to a 5-V system environment.
2OE
D
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
High-Impedance State During Power Up
and Power Down
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) DIPs
2Y4
1A1
1OE
VCC
D
SN54LVTZ240 . . . J PACKAGE
SN74LVTZ240 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low,
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVTZ240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVTZ240 is characterized for operation over the full military temperature range of − 55°C to 125°C.
The SN74LVTZ240 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
L
H
L
L
L
H
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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