MC14013B
Dual Type D Flip−Flop
The MC14013B dual type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each flip−flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flip−flops for counter and toggle applications.
http://onsemi.com
MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Flip−Flop Design
Logic state is retained indefinitely with clock level either high or
low; information is transferred to the output only on the
positive−going edge of the clock pulse
Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4013B
Pb−Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
VDD
Vin, Vout
Iin, Iout
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Value
Unit
−0.5 to +18.0
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
October, 2006 − Rev. 7
1
14
SOIC−14
D SUFFIX
CASE 751A
14013BG
AWLYWW
1
14
14
013B
ALYW G
G
TSSOP−14
DT SUFFIX
CASE 948G
V
Input or Output Current
(DC or Transient) per Pin
© Semiconductor Components Industries, LLC, 2006
MC14013BCP
AWLYYWWG
V
−0.5 to VDD + 0.5
14
PDIP−14
P SUFFIX
CASE 646
1
1
14
SOEIAJ−14
F SUFFIX
CASE 965
MC14013B
ALYWG
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC14013B/D
