MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
http://onsemi.com
MARKING
DIAGRAMS
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−power TTL Loads or One Low−power
•
•
•
•
14
PDIP−14
P SUFFIX
CASE 646
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
MC140xxBCP
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
140xxBG
AWLYWW
1
14
14
0xxB
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
MAXIMUM RATINGS (Voltages Referenced to VSS)
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
14
Unit
°C
VDD
Vin, Vout
Iin, Iout
VESD
Parameter
1
Value
Symbol
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
ESD Withstand Voltage
Human Body Model
Machine Model
Charged Device Model
V
> 3000
> 300
N/A
1
xx
= Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
DEVICE INFORMATION
Device
Description
1
Quad 2−Input NOR Gate
MC14011B
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
September, 2012 − Rev. 9
MC140xxB
ALYWG
MC14001B
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
© Semiconductor Components Industries, LLC, 2012
SOEIAJ−14
F SUFFIX
CASE 965
Quad 2−Input NAND Gate
MC14023B
Triple 3−Input NAND Gate
MC14025B
Triple 3−Input NOR Gate
MC14071B
Quad 2−Input OR Gate
MC14073B
Triple 3−Input AND Gate
MC14081B
Quad 2−Input AND Gate
MC14082B
Dual 4−Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Publication Order Number:
MC14001B/D
