MOTOROLA
Freescale Semiconductor, Inc.
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by MCM67B618A/D
SEMICONDUCTOR TECHNICAL DATA
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
MCM67B618A
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Single 5 V ± 5% Power Supply
Fast Access Times: 9/10/12 ns Max
Byte Writeable via Dual Write Enables
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
ADSP, ADSC, and ADV Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
3.3 V I/O Compatible
High Board Density 52–Lead PLCC Package
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENTS
A6
A7
E
UW
LW
ADSC
ADSP
ADV
K
G
A8
A9
A10
The MCM67B618A is a 1,179,648 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words
of 18 bits. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–edge–
triggered noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or
DQ9
address status cache controller (ADSC) input pins. Subsequent burst
DQ10
addresses can be generated internally by the MCM67B618A (burst
VCC
sequence imitates that of the i486 and Pentium) and controlled by the burst
VSS
address advance (ADV) input pin. The following pages provide more deDQ11
tailed information on burst controls.
DQ12
Write cycles are internally self–timed and are initiated by the rising edge
DQ13
of the clock (K) input. This feature eliminates complex off–chip write pulse
DQ14
generation and provides increased flexibility for incoming signals.
VSS
Dual write enables (LW and UW) are provided to allow individually writeVCC
able bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls
DQ15
DQ9 – DQ17 (the upper bits).
DQ16
DQ17
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information.
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
A5
A4
A3
A2
A1
A0
VSS
VCC
A15
A14
A13
A12
A11
Freescale Semiconductor, Inc...
With Burst Counter and Self–Timed Write
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the device.
i486 and Pentium are trademarks of Intel Corp.
REV 2
11/5/96
© Motorola, Inc. 1996
MOTOROLA FAST SRAM
For More Information On This Product,
Go to: www.freescale.com
MCM67B618A
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