MC74AC377
MC74ACT377
Octal D FlipĆFlop
with Clock Enable
OCTAL D
FLIP-FLOP WITH
CLOCK ENABLE
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP) input loads
all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time
before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop’s Q output. The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
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Ideal for Addressable Register Applications
Clock Enable for Address and Data Synchronization Applications
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Outputs Source/Sink 24 mA
See MC74AC273 for Master Reset Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
′ACT377 Has TTL Compatible Inputs
VCC
O7
D7
D6
O6
O5
D5
D4
O4
CP
20
19
18
17
16
15
14
13
12
N SUFFIX
CASE 738-03
PLASTIC
11
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
1
2
3
4
5
6
7
8
9
10
CE
O0
D0
D1
O1
O2
D2
D3
O3
GND
D0 D1 D2 D3 D4 D5 D6 D7
CP
PIN NAMES
D0–D7
CE
Q0–Q7
CP
CE
O0 O1 O2 O3 O4 O5 O6 O7
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
MODE SELECT-FUNCTION TABLE
Inputs
Outputs
Operating Mode
CP
Dn
Qn
L
Load ′1′
CE
H
H
Load ′0′
L
L
L
Hold (Do Nothing)
H
H
X
X
No Change
No Change
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
FACT DATA
5-1
