MPC750FACT/D
REV. 6
Fact Sheet
MOTOROLA POWERPC 750™ AND
POWERPC 740™ MICROPROCESSORS
The PowerPC 750 and PowerPC 740 microprocessors are low-power 32-bit implementations of the
PowerPC Reduced Instruction Set Computer (RISC) architecture. The PowerPC 750 and the PowerPC 740
microprocessors differ only in that the PowerPC 750 features a dedicated L2 cache interface with on-chip L2
tags. Both are software-compatible and bus-compatible with the PowerPC 603e™ and MPC7400 microprocessors, and the PowerPC 740 is pin-compatible as well. PowerPC 750/740 microprocessors are fully
JTAG-compliant.
Motorola PowerPC 750
Microprocessor
Superscalar Microprocessor
The PowerPC 750/740 microprocessors are superscalar, capable
of issuing three instructions per clock cycle into six independent
execution units:
I
I
I
I
I
Two integer units
Load/store unit
Floating-point unit
System register unit
Branch processing unit
The ability to execute multiple instructions in parallel, to
pipeline instructions, and the use of simple instructions with
rapid execution times yields maximum efficiency and throughput
for PowerPC 750/740 systems.
Power Management
The PowerPC 750/740 microprocessors feature a lowpower 2.6-volt or 1.9-volt design with three powersaving modes—doze, nap and sleep. These
user-programmable modes progressively reduce the
power drawn by the processor.
These low-power microprocessors offer dynamic
power management to selectively activate functional
units as they are needed by the executing instructions.
Both microprocessors also provide a thermal assist unit
and instruction cache throttling for softwarecontrollable thermal management.
PowerPC 750/740 Microprocessor
Block Diagram
System Register
Unit
Integer Integer
Unit
Unit
Branch Processing
Unit
Instruction
Unit
Floating Point
Unit
Load/Store
Unit
MMU
Data Cache
MMU
Inst. Cache
Cache and MMU Support
The PowerPC 750/740 microprocessors have separate
32-Kbyte, physically-addressed instruction and data
caches. Both caches are eight-way set-associative.
The additional dedicated L2 cache interface with onchip L2 tags (shown at right) is provided only by the
Bus Interface Unit
64b
Data
L2 Control / Tags
32b
Address
System Bus
64b
Data
17b
Address
L2 Cache
MPC750 Only
