MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Low Voltage 1:9 Clock
Distribution Chip
Freescale Semiconductor, Inc...
The MPC947 is a 1:9 low voltage clock distribution chip. The device
features the capability to select between two LVTTL compatible inputs
and fans the signal out to 9 LVCMOS or LVTTL compatible outputs.
These 9 outputs were designed and optimized to drive 50Ω series terminated transmission lines. With output–to–output skews of 500ps, the
MPC947 is ideal as a clock distribution chip for synchronous systems
which need a tight level of skew at a relatively low cost. For a similar
product targeted at a higher price/performance point, consult the
MPC948 data sheet.
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MPC947
LOW VOLTAGE
1:9 CLOCK
DISTRIBUTION CHIP
2 Selectable LVCMOS/LVTTL Clock Inputs
500ps Maximum Output–to–Output Skew
Drives Up to 18 Independent Clock Lines
Maximum Output Frequency of 110MHz
Synchronous Output Enable
Tristatable Outputs
32–Lead LQFP Packaging
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
3.3V VCC Supply Voltage
With an output impedance of approximately 7Ω, in both the HIGH and
LOW logic states, the output buffers of the MPC947 are ideal for driving
series terminated transmission lines. More specifically, each of the 9
MPC947 outputs can drive two series terminated 50Ω transmission lines.
With this capability, the MPC947 has an effective fanout of 1:18 in applications using point–to–point distribution schemes. With this level of
fanout, the MPC947 provides enough copies of low skew clocks for high
performance synchronous systems, including use as a clock distribution
chip for the L2 cache of a PowerPC 620 based system.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the select input pulled HIGH, the
TTL_CLK1 input will be selected.
All of the control inputs are LVCMOS/LVTTL compatible. The MPC947 provides a synchronous output enable control to allow
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into
high impedance. Note that all of the MPC947 inputs have internal pullup resistors.
The MPC947 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
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Go to: www.freescale.com
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