128Mb: x4, x8, x16 SDRAM
Features
SDRAM
MT48LC32M4A2 – 8 Meg x 4 x 4 banks
MT48LC16M8A2 – 4 Meg x 8 x 4 banks
MT48LC8M16A2 – 2 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web site: www.micron.com/dram
Features
Figure 1:
• PC100-, and PC133-compliant
• Fully synchronous; all signals registered on positive edge
of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge, and
auto refresh modes
• Self refresh mode; standard and low power
• 64ms, 8,192-cycle refresh (15.625µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3 ±0.3V power supply
Options
Notes:
1.
2.
3.
4.
x4 x8 x16
NC
DQ0
NC
NC
NC
DQ1
NC
NC
-
32M4
16M8
8M16
A2
Notes:
TG
P
FB3
BB 3
VDD
DQ0 DQ0
- VDDQ
NC DQ1
DQ1 DQ2
- VssQ
NC DQ3
DQ2 DQ4
- VDDQ
NC DQ5
DQ3 DQ6
- VssQ
NC DQ7
VDD
NC DQML
- WE#
- CAS#
- RAS#
CS#
BA0
BA1
A10
A0
A1
A2
A3
VDD
-
x16 x8 x4
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Vss
DQ15 DQ7
VssQ DQ14 NC
DQ13 DQ6
VDDQ DQ12 NC
DQ11 DQ5
VssQ DQ10 NC
DQ9 DQ4
VDDQ DQ8 NC
Vss
NC
DQMH DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
-
NC
NC
DQ3
NC
NC
NC
DQ2
NC
DQM
-
1. The # symbol indicates signal is active LOW. A dash (–) indicates
x8 and x4 pin function is same as x16 pin function.
Table 1:
Address Table
32 Meg x 4
F44
16 Meg x 8
8 Meg x 16
8 Meg x 4 x 4
banks
Configuration
B44
4 Meg x 8 x 4
banks
2 Meg x 16 x 4
banks
4K
4K
4K
Row addressing
4K (A0–A11)
4K (A0–A11)
4K (A0–A11)
Bank addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
2K (A0–A9,
A11)
1K (A0–A9)
512 (A0–A8)
Refresh count
-75
-7E
-6A
Column addressing
Table 2:
None
L
:G
Key Timing Parameters
CL = CAS (Read) latency
Access Time
Speed
Grade
CL = 2
CL = 3
Setup
Time
167 MHz
–
5.4ns
1.5ns
0.8ns
-7E
143 MHz
–
5.4ns
1.5ns
0.8ns
-7E
133 MHz
5.4ns
–
1.5ns
0.8ns
-75
133 MHz
–
5.4ns
1.5ns
0.8ns
-75
1
Clock
Frequency
-6A
None
IT3
Refer to Micron Technical Note: TN-48-05.
Off-center parting line.
Consult Micron for availability.
x16 only.
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_1.fm - Rev. L 5/06 EN
-
NC
Designator
• Configurations
– 32 Meg x 4 (8 Meg x 4 x 4 banks)
– 16 Meg x 8 (4 Meg x 8 x 4 banks)
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Write recovery (tWR)
– tWR = “2 CLK”1
• Package/Pinout
– Plastic package – OCPL2
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Lead-free
– 60-ball FBGA (8mm x 16mm)
– 60-ball FBGA (8mm x 16mm)
Lead-free
– 54-ball VFBGA (8mm x 8mm)
– 54-ball VFBGA (8mm x 8mm)
Lead-free
• Timing (cycle time)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– 6.0ns @ CL = 3 (x16 only)
• Self refresh
– Standard
– Low power
• Design revision
• Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
54-Pin TSOP Pin Assignment
(Top View)
Hold
Time
100 MHz
6ns
–
1.5ns
0.8ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
