4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
DRAM
FEATURES
PIN ASSIGNMENT (Top View)
• Industry-standard x4 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
• Single power supply (+3.3V ±0.3V or +5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS
24/26-Pin TSOP
(DB-2)
24/26-Pin SOJ
(DA-2)
VCC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ4
DQ3
CAS#
OE#
A9
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
VCC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ4
DQ3
CAS#
OE#
A9
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
MARKING
• Voltages
3.3V
5V
* NC on 2K refresh and A11 on 4K refresh options.
Note: The “#” symbol indicates signal is active LOW.
LC
C
4 MEG x 4 EDO DRAM PART NUMBERS
• Refresh Addressing
2,048 (i.e. 2K) Rows
4,096 (i.e. 4K) Rows
E8
E9
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
PART NUMBER
MT4LC4M4E8DJ
MT4LC4M4E8DJS
MT4LC4M4E8TG
MT4LC4M4E8TGS
MT4LC4M4E9DJ
MT4LC4M4E9DJS
MT4LC4M4E9TG
MT4LC4M4E9TGS
MT4C4M4E8DJ
MT4C4M4E8DJS
MT4C4M4E8TG
MT4C4M4E8TGS
MT4C4M4E9DJ
MT4C4M4E9DJS
MT4C4M4E9TG
MT4C4M4E9TGS
None
S
• Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
Vcc
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
5V
REFRESH
2K
2K
2K
2K
4K
4K
4K
4K
2K
2K
2K
2K
4K
4K
4K
4K
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
KEY TIMING PARAMETERS
SPEED
-5
-6
tRC
tRAC
tPC
tAA
t CAC
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
GENERAL DESCRIPTION
tCAS
8ns
10ns
4 Meg x 4 EDO DRAM
D47.pm5 – Rev. 3/97
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1997, Micron Technology, Inc.
