OBSOLETE
4 MEG x 4
EDO DRAM
MT4LC4M4E8, MT4LC4M4E9
DRAM
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html
FEATURES
PIN ASSIGNMENT (Top View)
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance, low-power CMOS silicon-gate
process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR)
• Optional self refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access
OPTIONS
VDD
DQ0
DQ1
WE#
RAS#
**NC/A11
A10
A0
A1
A2
A3
VDD
MARKING
• Refresh Addressing
2,048 (2K) rows
4,096 (4K) rows
E8
E9
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
DJ
TG
• Timing
50ns access
60ns access
-5
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
NOTE:
26
25
24
23
22
21
VDD
VSS
DQ0
DQ3
DQ1
DQ2
WE#
CAS#
RAS#
OE#
**NC/A11
A9
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
26
25
24
23
22
21
VSS
DQ3
DQ2
CAS#
OE#
A9
8
9
10
11
12
13
19
18
17
16
15
14
A8
A7
A6
A5
A4
VSS
4 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER
MT4LC4M4E8DJ-x
MT4LC4M4E8DJ-x S
MT4LC4M4E8TG-x
MT4LC4M4E8TG-x S
MT4LC4M4E9DJ-x
MT4LC4M4E9DJ-x S
MT4LC4M4E9TG-x
MT4LC4M4E9TG-x S
None
S*
1. The 4 Meg x 4 EDO DRAM base number differentiates the
offerings in one place - MT4LC4M4E8. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9
designates a 4K refresh for EDO DRAMs.
2. The “#” symbol indicates signal is active LOW.
REFRESH
ADDRESSING
PACKAGE
REFRESH
2K
2K
2K
2K
4K
4K
4K
4K
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
x = speed
KEY TIMING PARAMETERS
tRC
tRAC
tPC
t AA
t CAC
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
(the latter 11 bits for 2K and the latter 10 bits for 4K; address
pins A10 and A11 are “Don’t Care”). READ and WRITE
cycles are selected with the WE# input.
A logic HIGH on WE# dictates read mode, while a logic
LOW on WE# dictates write mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE# or CAS#,
whichever occurs last. An EARLY WRITE occurs when
WE# is taken LOW prior to CAS# falling. A LATE WRITE or
READ-MODIFY-WRITE occurs when WE# falls after CAS#
is taken LOW. During EARLY WRITE cycles, the data
outputs (Q) will remain High-Z regardless of the state of
OE#. During LATE WRITE or READ-MODIFY-WRITE
tCAS
8ns
10ns
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
4 Meg x 4 EDO DRAM
D47.p65 – Rev. 6/98
1
2
3
4
5
6
** NC on 2K refresh and A11 on 4K refresh options.
*Contact factory for availability
SPEED
-5
-6
24/26-Pin TSOP
24/26-Pin SOJ
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
