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MT4LC8M8C2-5D

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OBSOLETE 8 MEG x 8 FPM DRAM MT4LC8M8E1, MT4LC8M8B6 DRAM For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/dramds.html FEATURES PIN ASSIGNMENT (Top View) • Single +3.3V ±0.3V power supply • Industry-standard x8 pinout, timing, functions, and packages • 13 row, 10 column addresses (E1) or 12 row, 11 column addresses (B6) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTLcompatible • FAST PAGE MODE (FPM) access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention OPTIONS VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC MARKING • Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows B6 E1 • Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) DJ TG VSS DQ7 DQ6 DQ5 DQ4 Vss CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS VCC DQ0 DQ1 DQ2 DQ3 NC VCC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS DQ7 DQ6 DQ5 DQ4 VSS CAS# OE# NC/A12** A11 A10 A9 A8 A7 A6 VSS 8 MEG x 8 FPM DRAM PART NUMBERS MT4LC8M8E1DJ-x MT4LC8M8E1DJ-x S MT4LC8M8E1TG-x MT4LC8M8E1TG-x S MT4LC8M8B6DJ-x MT4LC8M8B6DJ-x S MT4LC8M8B6TG-x MT4LC8M8B6TG-x S None S* NOTE: 1. The 8 Meg x 8 FPM DRAM base number differentiates the offerings in one place— MT4LC8M8E1. The fifth field distinguishes various options: E1 designates an 8K refresh and B6 designates a 4K refresh for FPM DRAMs. 2. The # symbol indicates signal is active LOW. KEY TIMING PARAMETERS tPC tAA tCAC 90ns 110ns 50ns 60ns 30ns 35ns 25ns 30ns PACKAGE REFRESH SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP Standard Self Standard Self Standard Self Standard Self The 8 Meg x 8 DRAMs are high-speed CMOS, dynamic random-access memory devices containing 67,108,864 bits organized in a x8 configuration. The 8 Meg x 8 DRAMs are functionally organized as 8,388,608 locations containing eight bits each. The 8,388,608 memory locations are arranged in 8,192 rows by 1,024 columns for the MT4LC8M8E1 or 4,096 rows by 2,048 columns for the MT4LC8M8B6. During READ or WRITE cycles, each location is uniquely addressed via the address bits. First, the row address is latched by the Part Number Example: tRAC 8K 8K 8K 8K 4K 4K 4K 4K GENERAL DESCRIPTION MT4LC8M8E1DJ-5 tRC REFRESH ADDRESSING x = speed *Contact factory for availability 13ns 15ns 8 Meg x 8 FPM DRAM D19_2.p65 – Rev. 5/00 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 **A12 on E1 version, NC on B6 version -5 -6 • Refresh Rates Standard Refresh (64ms period) Self Refresh (128ms period) SPEED -5 -6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PART NUMBER • Timing 50ns access 60ns access 32-Pin TSOP 32-Pin SOJ 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc.

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