MT9042C
Multitrunk System Synchronizer
Data Sheet
Features
•
November 2005
Meets jitter requirements for: AT&T TR62411
Stratum 3, 4 and Stratum 4 Enhanced for DS1
interfaces; and for ETSI ETS 300 011, TBR 4,
TBR 12 and TBR 13 for E1 interfaces
Ordering Information
•
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
•
Provides 8 kHz ST-BUS framing signals
•
MT9042CP
MT9042CPR
MT9042CP1
MT9042CPR1
Selectable 1.544 MHz, 2.048 MHz or 8 kHz
input reference signals
Provides bit error free reference switching meets phase slope and MTIE requirements
•
Operates in either Normal, Holdover and
Freerun modes
The MT9042C Multitrunk System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links.
The MT9042C generates ST-BUS clock and framing
signals that are phase locked to either a 2.048 MHz,
1.544 MHz, or 8 kHz input reference.
Applications
The MT9042C is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011.
It will meet the jitter tolerance, jitter transfer, intrinsic
jitter, frequency accuracy, holdover accuracy, capture
range, phase slope and MTIE requirements for these
specifications.
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
TRST
OSCi
OSCo
PRI
SEC
Reference
Select
MUX
Reference
RSEL
LOS1
LOS2
VDD
TIE
Corrector
Circuit
Master
Clock
DPLL
Output
Interface
Circuit
State
Select
Input
Impairment
Monitor
State
Select
Feedback
Automatic/Manual
Control State Machine
MS1
MS2
VSS
Virtual
Reference
Selected
Reference
TIE
Correcto
r Enable
Tubes
Tape & Reel
Tubes
Tape & Reel
-40°C to +85°C
•
•
PLCC
PLCC
PLCC*
PLCC*
Description
Accepts reference inputs from two independent
sources
•
Pin
Pin
Pin
Pin
*Pb Free Matte Tin
•
•
28
28
28
28
Frequency
Select
MUX
Guard Time
Circuit
RST
GTo
GTi
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
