CMOS ST-BUSTM Family
MT90820
Large Digital Switch
Data Sheet
Features
August 2005
•
2,048 × 2,048 channel non-blocking switching at
8.192 Mb/s
•
Per-channel variable or constant throughput
delay
•
Automatic identification of ST-BUS/GCI interfaces
•
Accept ST-BUS streams of 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s
•
Automatic frame offset delay measurement
•
Per-stream frame delay offset programming
•
Per-channel high impedance output control
Applications
•
Per-channel message mode
•
Medium and large switching platforms
•
Control interface compatible to Motorola nonmulitplexed CPUs
•
CTI application
•
Connection memory block programming
•
Voice/data multiplexer
•
IEEE-1149.1 (JTAG) Test Port
•
Digital cross connects
•
ST-BUS/GCI interface functions
•
Support IEEE 802.9a standard
VDD VSS
TMS
TDI
Ordering Information
MT90820AP
84 Pin PLCC
MT90820AL
100 Pin MQFP
MT90820APR
84 Pin PLCC
MT90820AL1
100 Pin MQFP*
MT90820AP1
84 Pin PLCC*
MT90820APR1 84 Pin PLCC*
*Pb Free Matte Tin
Tubes
Trays
Tape & Reel
Trays
Tubes
Tape & Reel
-40°C to +85°C
TDO
TCK
TRST
IC
RESET
ODE
Test Port
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
Loopback
Serial
Parallel
to
Parallel
Output
MUX
Multiple Buffer
Data Memory
Converter
Timing
Unit
F0i
Serial
Converter
Connection
Memory
Internal
Registers
CLK
to
FE/ WFPS
HCLK
Microprocessor Interface
AS/ IM DS/ CS
ALE
RD
R/W
/WR
A7-A0 DTA D15-D8/ CSTo
AD7-AD0
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2000-2005, Zarlink Semiconductor Inc. All Rights Reserved.
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
