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by MTD2955E/D
SEMICONDUCTOR TECHNICAL DATA
™ Data Sheet
TMOS E-FET.™
Power Field Effect Transistor
DPAK for Surface Mount
Designer's
MTD2955E
Motorola Preferred Device
P–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
12 AMPERES
60 VOLTS
RDS(on) = 0.3 OHM
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
• Replaces the MTD2955
®
D
G
CASE 369A–13, Style 2
DPAK
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
VDSS
60
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
± 25
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
12
7.0
36
Adc
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
PD
75
0.6
1.75
Watts
W/°C
Watts
Rating
Apk
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 3.0 mH, RG = 25 Ω)
EAS
216
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
RθJC
RθJA
RθJA
1.67
100
71.4
°C/W
TL
260
°C
Operating and Storage Temperature Range
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
© Motorola TMOS
Motorola, Inc. 1995
Power MOSFET Transistor Device Data
1
