Data Addendum
January 2002
ORCA® OR3LxxxB Series
Field-Programmable Gate Arrays
Introduction
This data addendum refers to the information found
in the ORCA® Series 3C and 3T Field-Programmable
Gate Arrays Data Sheet.
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Features
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High-performance, cost-effective, 0.25 µm 5-level
metal technology.
2.5 V internal supply voltage and 3.3 V I/O supply
voltage for speed and compatibility.
Up to 340,000 usable gates‡ in 0.25 µm.
Up to 612 user I/Os in 0.25 µm. (OR3LxxxB I/Os
are 5 V tolerant to allow interconnection to both
3.3 V and 5 V devices, selectable on a per-pin
basis, when using 3.3 V I/O supply.)
Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables (LUTs)
per PFU, organized in two nibbles for use in nibbleor byte-wide functions. Allows for mixed arithmetic
and logic functions in a single PFU.
Nine user registers per PFU, one following each
LUT, plus one extra. All have programmable clock
enable and local set/reset, plus a global set/reset
that can be disabled per PFU.
Flexible input structure (FINS) of the PFUs provides a routability enhancement for LUTs with
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shared inputs and the logic flexibility of LUTs with
independent inputs.
Fast-carry logic and routing to adjacent PFUs for
nibble-wide, byte-wide, or longer arithmetic functions, with the option to register the PFU carry-out.
Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each programmable logic cell (PLC).
Abundant hierarchical routing resources based on
routing two data nibbles and two control lines per
set provide for faster place and route implementations and less routing delay.
Individually programmable drive capability: 12 mA
sink/6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan (IEEE † 1149.1 JTAG) and
testability function to 3-state all I/O pins.
Enhanced system clock routing for low-skew, highspeed clocks originating on-chip or at any I/O.
Up to four ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to
internal general clock routing.
StopCLK feature to glitchlessly stop/start the
ExpressCLKs independently by user command.
* PAL is a trademark of Lattice Semiconductor
† IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA OR3LxxxB Series FPGAs
Device
System
Gates‡
LUTs
Registers
Max User
RAM
OR3L165B
OR3L225B
120K—244K
166K—340K
8192
11552
10752
14820
131K
185K
User I/Os Array Size
516
612
32 × 32
38 × 38
Process
Technology
0.25 µm/5 LM
0.25 µm/5 LM
‡ The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 × 4 RAM
(or 512 gates) per PFU.
