Preliminary Data Sheet, Rev. 1
September 1998
ORCA® Series 3
Field-Programmable Gate Arrays
T Abundant hierarchical routing resources based on rout-
Features
T High-performance, cost-effective, 0.35 µm (OR3C) and
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0.3 µm (OR3T) 4-level metal technology, with a migration plan to 0.25 µm technology (4- or 5-input look-up
table delay of 1.7 ns with -5 speed grade in 0.35 µm).
Up to 186,000 usable gates in 0.3 µm, expanding to
320,000 usable gates in 0.25 µm.
Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
New twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be disabled per PFU.
New flexible input structure (FINS) of the PFUs provides
a routability enhancement for LUTs with shared inputs
and the logic flexibility of LUTs with independent inputs.
Fast-carry logic and routing to adjacent PFUs for
nibble-, byte-wide, or longer arithmetic functions, with
the new option to register the PFU carry-out.
New softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
New supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder, and
PAL*-like AND-OR with optional INVERT in each programmable logic cell (PLC).
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ing two data nibbles and two control lines per set provide
for faster place and route implementations and less routing delay.
TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
Individually programmable drive capability: 12 mA sink/
6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan (IEEE †1149.1 JTAG) and
3-state all I/O pins (TS_ALL) testability functions.
Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
Up to four new ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to internal general clock routing.
New StopCLK feature to glitchlessly stop/start ExpressCLKs independently by user command.
New programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF)
latch for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
* PAL is a trademark of Advanced Micro Devices, Inc.
† IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. ORCA Series 3 FPGAs
Device
Usable Gates‡
Max
Registers
Max User
RAM Bits
Max
User I/Os
Array Size
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
OR3T165
18K—36K
24K—48K
40K—80K
58K—116K
92K—186K
120K—244K
1872
2436
3780
5412
8400
10752
18K
25K
41K
62K
100K
131K
192
224
288
352
448
512
12 x 12
14 x 14
18 x 18
22 x 22
28 x 28
32 x 32
‡ The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
