This is an abbreviated data sheet. Contact a Cypress
representative for complete specifications.
USE ULTRA37000TM FOR
PALC22V10
ALL NEW DESIGNS
Reprogrammable CMOS
PAL® Device
Features
• 20, 25, 35 ns commercial and industrial
• 25, 30, 40 ns military
• Advanced second-generation PAL® architecture
• Up to 22 input terms and 10 outputs
• Low power
• High reliability
— 55 mA max. “L”
— Proven EPROM technology
— 90 mA max. standard
— 100% programming and functional testing
— 120 mA max. military
• Windowed DIP, windowed LCC, DIP, LCC, and PLCC
available
• CMOS EPROM technology for reprogrammability
• Variable product terms
Functional Description
— 2 x (8 through 16) product terms
• User-programmable macrocell
The Cypress PALC22V10 is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a
new concept, the “programmable macrocell.”
— Output polarity control
— Individually selectable for registered or
combinatorial operation
Logic Block Diagram (PDIP/CDIP)
VSS
I
I
I
I
I
I
I
I
I
CP/I
11
12
I
10
9
8
7
6
5
4
3
2
1
14
12
10
Macrocell
Macrocell
Macrocell
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
Macrocell
Macrocell
Macrocell
16
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
14
15
16
17
18
19
20
21
22
23
24
I
I/O9
I/O8
I/O 7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
LCC/PLCC
Top View
I
I
CP/I
NC
VCC
I/O 0
I/O 1
Pin Configuration
4 3 2 1 282726
5
I
6
I
I
NC 7
8
9
I
10
I
11
I
25
24
23
22
21
20
19
I/O 2
I/O 3
I/O 4
NC
I/O 5
I/O 6
I/O 7
•
I/O 9
I/O 8
I
I
I
Cypress Semiconductor Corporation
Document #: 38-03052 Rev. *A
VSS
NC
12131415161718
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 9, 2004
