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PI74ALVCH162244A

製品説明
仕様・特性

PI74ALVCH162244 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 1 2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 16-Bit Buffer Driver with 3-State Outputs Product Features Product Description • • • • Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced using the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. • • • • • PI74ALVCH162244 is designed for low-voltage operation VCC = 2.3V to 3.6V Hysteresis on all inputs Typical VOLP (Output Ground Bounce) < 0.8V at VCC = 3.3V, TA = 25°C Typical VOHV (Output VOH Undershoot) < 2.0V at VCC = 3.3V, TA = 25°C Output ports have equivalent 26-Ohm series resistors: no external resistors are required Bus Hold retains last active bus state during 3-State, eliminating the need for external pullup resistors Industrial operation: –40°C to +85°C Packages available: – 48-pin 240 mil wide plastic TSSOP (A) – 48-pin 300 mil wide plastic SSOP (V) The PI74ALVCH162244 is an non-inverting 16-bit buffer/driver designed for low voltage 2.3V to 3.6V VCC operation. The buffer/driver is designed specifically to improve both the performance and density of 3-State memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides non-inverting outputs and symmetrical active-low output-enable (OE) inputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor in which the minimum value is determined by the current-sinking capability of the driver. The PI74ALVCH162244 has “Bus Hold” which retains the data input’s last state whenever the data input goes to high-impedance preventing “floating” inputs and eliminating the need for pullup/ down resistors. Logic Block Diagram 1OE 3OE 1A0 1Y0 3A0 3Y0 1A1 1Y1 3A1 3Y1 1A2 1Y2 3A2 3Y2 1A3 1Y3 3A3 3Y3 2OE 4OE 2A0 2Y0 4A0 4Y0 2A1 2Y1 4A1 4Y1 2A2 2Y2 4A2 4Y2 2A3 2Y3 4A3 4Y3 1 PS8092B 10/15/01

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