HD74HC74
Dual D-type Flip-Flops (with Preset and Clear)
REJ03D0549-0300
Rev.3.00
Oct 27, 2008
Description
The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the
data input is transferred to the output during the positive going transition to the clock pulse. Preset and clear are
independent of the clock and accomplished by a low level at the appropriate input.
Features
•
•
•
•
•
•
High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74HC74P
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
P
—
HD74HC74FPEL
SOP-14 pin (JEITA)
PRSP0014DF-B
(FP-14DAV)
FP
EL (2,000 pcs/reel)
HD74HC74RPEL
SOP-14 pin (JEDEC)
PRSP0014DE-A
(FP-14DNV)
RP
EL (2,500 pcs/reel)
HD74HC74TELL
TSSOP-14 pin
PTSP0014JA-B
(TTP-14DV)
T
ELL (2,000 pcs/reel)
Note:
Please consult the sales office for the above package availability.
Function Table
Inputs
Outputs
Q
Preset
Clock
Data
Q
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*1
H*1
H
H
H
H
L
H
H
H
L
L
H
L
X
No change
H
H
H
X
No change
H
H:
L:
X:
Note:
Clear
L
H
X
No change
H
High level
Low level
Irrelevant
1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and
Clear go High simultaneously.
REJ03D0549-0300 Rev.3.00 Oct 27, 2008
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