PF1163-01
SPC7281F
SPC7281F0A
0A
IEEE1394 LINK/ Transaction Controller
ary
min
eli
Pr
q SBP-2 LINK Engine on chip
q High-speed transfer(Ultra ATA33)
q Built-in CPU and Flash
s DESCRIPTION
The SPC7281F0A is an IEEE Standard 1394-1995, P1394a Draft2.1 compliant LINK/Transaction Controller.
Since some of the transaction functions of this controller have become hardware, the later PageTable fetch and
data transmission can be executed automatically by setting the PageTable address and size in SBP-2.
In addition, thanks to a built-in MPU (SEIKO EPSON’s original 32-bit RISC processor C33) called a Flash ROM
which is necessary for the conversion system, the controller can provide peripheral devices with the optimum
1394 interfaces by simply adding a Cable PHY Transceiver/Arbiter that complies with the standard.
s FEATURES
q LINK/Transaction Controller
• All interactive data transmissions in both asynchronous and isochronous transfer modes are supported.
• Stable interactive data transmissions of 100 Mbps, 200 Mbps and 400 Mbps of MaxPayload were made
possible by the built-in SRAM.
• The hardware can detect IsocronousResourceManager automatically.
• Some of the transaction functions have become hardware to prevent the actual data transmission rate
from declining due to overhead (to secure the dedicated partition).
• Communication with the upper layers has been simplified by separating the header and data partitions.
• The data partition has been subdivided into Stream and ORB partitions.
• A ring buffer is employed for the recipient header, recipient data (recipient Stream and recipient ORB
partitions) and sending data partitions.
• The sizes of all partitions can be set freely.
• The busy state during data reception is controlled by the hardware automatically.
q SBP-2 Support
By setting the PageTable address and size in SBP-2, the later Page Table fetch and data transmission can
be executed automatically.
q PHY/LINK Interface
The P1394a is supported.
Transmission rate 100/200/400 Mbps are supported.
Isolation is supported (a bus holder is built in).
q CPU
SEIKO EPSON’s original 32-bit Microsoft Controller Unit is built in.
Booting using both internal and external Flash ROMs is possible.
q IDE Interface
PIO mode 0/1/2/3/4, Multiword DMA mode 0/1/2 and Ultra-DMA mode 0/1/2 are supported.
q Built-in SRAM
An 8-Kbyte SRAM is built in.
q Built-in Flash ROM
An 64-Kbyte Flash ROM is built-in.
q 3.3 V/ 5.0 V power supply
q 184-pin flat package (Pin pitch: 0.4 mm)
s The package is not designed to be radiation-proof.
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