MOTOROLA
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by MCM67Q709A/D
SEMICONDUCTOR TECHNICAL DATA
MCM67Q709A
128K x 9 Bit Separate I/O
Synchronous Fast Static RAM
The MCM67Q709A is a 1,179,648–bit static random access memory,
organized as 131,072 words of 9 bits. It features separate TTL input and output
buffers, which drive 3.3 V output levels and incorporates input and output registers on–board with high speed SRAM. It also features transparent–write and data
pass–through capabilities.
The synchronous design allows for precise cycle control with the use of an
external single clock (K). The addresses (A0 – A16), data input (D0 – D8), data
output (Q0 – Q8), write enable (W), chip enable (E), and output enable (G), are
registered in on the rising edge of clock (K).
The control pins (E, W, G) function differently in comparison to most synchronous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
The pass–through function is always enabled. E high disables the write to the
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
The MCM67Q709A is available in an 86–bump surface mount PBGA (Plastic
Ball Grid Array) package.
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Single 5 V ± 5% Power Supply
Fast Cycle Time: 10 ns Max
Single Clock Operation
TTL Input and Output Levels (Outputs LVTTL Compatible)
Address, Data Input, E, W, G Registers On–Chip
100 MHz Maximum Clock Cycle Time
Self–Timed Write
Separate Data Input and Output Pins
Transparent–Write and Pass–Through
High Output Drive Capability: 50 pF/Output at Rated Access Time
Boundary Scan Implementation
86–Bump PBGA Package for High Speed Operation
ZP PACKAGE
PBGA
CASE 896A–02
PIN NAMES
A0 – A16 . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
D0 – D8 . . . . . . . . . . . . . . . . . . . . Data Inputs
Q0 – Q8 . . . . . . . . . . . . . . . . . . Data Outputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
SCK . . . . . . . . . . . . . . . . . . Scan Clock Input
SE . . . . . . . . . . . . . . . . . . . . . . . Scan Enable
SDI . . . . . . . . . . . . . . . . . . . . Scan Data Input
SDO . . . . . . . . . . . . . . . . . Scan Data Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
PIN ASSIGNMENT
1
4
5
6
7
8
VCC SDI SDO
A4
A0
VSS
A2
9
2
3
E
W
A16
A14
G
C
D7
A15
NC
VSS VSS VSS VSS
Q8 VSS
D
VSS
Q7
VSS
VSS VSS VSS VSS
Q6
D5
VSS VSS
VSS VSS VSS VSS
VSS VCC
VSS VSS VSS VSS
D4
Q4
Q2
A
B
E
F
G
H
J
K
K
A6
VSS D8
D6
VCC
Q5
VSS
D3
Q3
VSS VSS
VSS VSS VSS
D2
VSS
D1
NC VSS
VSS VSS VSS
D0 VSS
Q1
A12
A10 VSS
A13
A11
A9
A8
A5
A1
SCK VCC SE
A7
A3
TOP VIEW
Q0
Not to Scale
REV 3
8/13/99
© Motorola, Inc. 1999
MOTOROLA FAST SRAM
MCM67Q709A
1
