P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Three-State Output
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
– 15/20/25/35/45/55/70/85 ns (Military)
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
Low Power Operation
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C187L)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
Separate Data I/O
DESCRIPTION
The P4C187/P4C187L are 65, 536-bit ultra high speed static
RAMs organized as 64K x 1. The CMOS memories require
no clocks or refreshing and have equal access and cycle
times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply
voltages down to 2.0V for the Low Power version, typically
drawing 10µA.
Access times as fast as 10 nanoseconds are available,
Functional Block Diagram
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
P4C187L.
The P4C187/P4C187L are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages providing excellent board level densities.
Pin ConfigurationS
DIP (P3, D3, C3)
SOJ (J4)
LCC configurations at end of datasheet
Document # SRAM111 REV D
Revised October 2013
