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74HC174N
74HC174; 74HCT174 Hex D-type flip-flop with reset; positive-edge trigger Rev. 4 — 12 May 2016 Product data sheet 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Input levels: For 74HC174: CMOS level For 74HCT174: TTL level Six edge-triggered D-type flip-flops Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V. Multiple package options Specified from 40 C to +85 C and 40 C to +125 C. 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC174D Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HCT174D 74HC174DB 74HCT174DB 74HC174PW 74HCT174PW SOT338-1 SOT403-1
TI
Texas Instruments Incorporated
U.S.A
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