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BUK582-60A
Philips Semiconductors Product Specification PowerMOS transistor Logic level FET BUK582-60A GENERAL DESCRIPTION QUICK REFERENCE DATA N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in automotive and general purpose switching applications. SYMBOL PIN MAX. UNIT VDS ID Ptot Tj RDS(ON) PINNING - SOT223 PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V 60 2.5 1.7 150 0.15 V A W ˚C Ω PIN CONFIGURATION DESCRIPTION 1 drain 3 source 4 d 4 gate 2 SYMBOL drain (tab) g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ID ID IDM Ptot Tstg Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature RGS = 20 kΩ Tamb = 25 ˚C Tamb = 100 ˚C Tamb = 25 ˚C Tamb = 25 ˚C - - 55 - 60 60 15 2.5 1.5 10 1.7 150 150 V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL Rth j-b Rth j-amb PARAMETER CONDITIONS 1 From junction to board From junction to ambient Mounted on any PCB e.g. Fig.18 Mounted on PCB of Fig.18 MIN. TYP. MAX. UNIT - 40 - 75 K/W K/W 1 Temperature measured 1-3 mm from tab. April 1993 1 Rev 1.000
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