Philips Semiconductors
Product specification
TrenchMOS™ transistor
Standard level FET
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope
suitable for surface mounting. Using
’trench’ technology the device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in automotive and
general
purpose
switching
applications.
PINNING - SOT404
PIN
BUK7614-55
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 10 V
PIN CONFIGURATION
MAX.
UNIT
55
68
142
175
14
V
A
W
˚C
mΩ
SYMBOL
DESCRIPTION
d
mb
1
gate
2
drain
3
source
mb
drain
g
2
1
s
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
55
55
16
68
48
240
142
175
V
V
V
A
A
A
W
˚C
MIN.
MAX.
UNIT
-
2
kV
TYP.
MAX.
UNIT
-
1.05
K/W
50
-
K/W
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-
Rth j-a
April 1998
Minimum footprint, FR4
board
1
Rev 1.000
