SCR050 Product Brief
3.3V and 5V TTL, Low Jitter PLL Module with Internal VCXO
Description
The SCR050 series offers a versatile PLL solution with an
embedded high-performance VCXO for use in networking and
telecommunications applications. The SCR050 module performs
clock recovery and data retiming (CDR), jitter filtering of an
input clock signal, or frequency translation to meet the specific
requirements of a given application.
Features
▪ Integrated PLL with quartz-stabilized VCXO
▪ User-defined PLL loop response
▪ Input data rates from 8 kbps to 65 kbps, TTL compatible
▪ Two-frequency output with Tri-state control
▪ Recovered clock & data outputs, TTL compatible
▪ NRZ data compatible
▪ Loss of Signal (LOS) status alarm with automatic free-run
switching
▪ Input control for forced free-run operating mode
▪ Rugged, shielded FR4 package available in thru-hole and true
SMD
Applications
▪ CDR for T1/E1 and T3/E3 equipment
▪ CDR for video distribution systems
▪ CDR for telemetric/satellite systems
▪ Frequency translation (step-up) of a reference signal for
synchronous applications
▪ Jitter filtering of a distributed or recovered clock signal
LOSIN
HIZ
Phase Detector
& LOS Circuit
Specification
Input data rate (NRZ)
8 kbps to 65.536 Mbps
Input data rate (RZ)
8 kbps to 32.768 Mbps
Operating Frequency
(CLK1)
12 to 65.536 MHz (as specified)
0.05 to 32.768 MHz (as specified)
+/-20 ppM through +/-100 ppM max (as specified)
over all conditions including operating
temperature, calibration tolerance, rated input
(supply) voltage, load changes, aging*, shock and
vibration
10 years @ 40°C average ambient operating
temperature
*Aging:
OPP
OpA
OPOUT
www.saronix.com
+/-20 ppM through +/-100 ppM min (as specified)
Input Lock Acquisition
Time
15ms typ
Supply Voltage
3.3V or 5V (7V absolute max) (as specified)
Output Logic
TTL compatible, 5 TTL load
5ns max (measured between 0.5 and 2.5V)
> 50dB (RDATA, RCLK)
Jitter generation
< 0.001 UI (when locked to input)
Phase (computed) jitter
CLK2
0 to +70°C or –40 to +85°C (as specified)
Track and hold range
Jitter attenuation
RDAT A
Operating Range
Rise/Fall Time
÷N
VC
Rev A.1
Parameter
RCLK
CLK1
PB-249
Performance Features
Free-Run Accuracy
DATA IN
LOS
PHO
OPN
Owing to unique invention, the SCR050 is an RFI-shielded
modular design set on an FR4 base, available with true SMD pads
or a molded leadframe, and featuring a body thickness less than
3.5mm. The SCR050 solution is mechanically interchangeable
and socket-compatible with similar devices available on the
market.
Operating Frequency
(CLK2)
Functional Block Diagram
CLK IN
The SCR050 device combines flexible IC functionality from
Pericom® with high-performance fundamental-mode quartz
VCXO technology from SaRonix™ into a single, modular
solution for ultra-low output jitter and fast acquisition of the
data/clock inputs. The TTL-compatible device features a userconfigurable loop filter to fine-tune the PLL response for the
particular application, output disable controls, and a Loss of
Signal (LOS) alarm.
0.7ps RMS (1-sigma) max, 12kHz to 40MHz
frequency band (free run mode)
