GS71116AGP/U
TSOP, FP-BGA
Commercial Temp
Industrial Temp
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
64K x 16
1Mb Asynchronous SRAM
Features
Fine Pitch BGA 64K x 16-Bump Configuration
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid
Array package
The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTLcompatible. The GS71116A is available in the 6 mm x 8 mm
Fine Pitch BGA and 400 mil TSOP Type-II packages.
Pin Descriptions
Symbol
Address input
DQ1–DQ16
Data input/output
CE
Chip enable input
LB
Lower byte enable input
(DQ1 to DQ8)
UB
Upper byte enable input
(DQ9 to DQ16)
WE
+3.3 V power supply
VSS
Ground
NC
5
6
A
LB
OE
A0
A1
A2
NC
B
DQ16
UB
A3
A4
CE
DQ1
C
DQ14 DQ15
A5
A6
DQ2
DQ3
D
VSS DQ13
NC
A7
DQ4
VDD
E
VDD DQ12
NC
NC
DQ5
VSS
F
DQ11 DQ10
A8
A9
DQ7
DQ6
DQ9
NC
A10
A11
WE
DQ8
H
NC
A12
A13
A14
A15
NC
6 mm x 8 mm, 0.75 mm Bump Pitch (Package U)
Top View
TSOP-II 64K x 16-Pin Configuration
VSS
Output enable input
VDD
4
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A12
NC
Write enable input
OE
3
A4
A3
A2
A1
A0
CE
DQ1
DQ2
DQ3
DQ4
VDD
Description
A0–A15
2
G
Description
1
No connect
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Top view
44-pin
TSOP II
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
16
17
18
19
20
21
22
A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NC
Package TP
Rev: 1.10 1/2013
1/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
